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IDT2305 3.3V ZERO DELAY CLOCK BUFFER
COMMERCIALAND INDUSTRIAL TEMPERATURE RANGES
3.3V ZERO DELAY CLOCK BUFFER
FEATURES:
* * * * * * * * * * * * * Phase-Lock Loop Clock Distribution 10MHz to 133MHz operating frequency Distributes one clock input to one bank of five outputs Zero Input-Output Delay Output Skew < 250ps Low jitter < 200ps cycle-to-cycle IDT2305-1 for Standard Drive IDT2305-1H for High Drive Industrial Temperature Available No external RC network required Operates at 3.3V VDD Available in SOIC package Power Down Mode
IDT2305
DESCRIPTION:
The IDT2305 is a high-speed phase-lock loop (PLL) clock buffer, designed to address high-speed clock distribution applications. The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range of 10 to 133MHz. The IDT2305 is an 8-pin version of the IDT2309. IDT2305 accepts one reference input, and drives out five low skew clocks. The -1H version of this device operates, up to 133MHz frequency and has a higher drive than the -1 device. All parts have on-chip PLLs which lock to an input clock on the REF pin. The PLL feedback is on-chip and is obtained from the CLKOUT pad. In the absence of an input clock, the IDT2305 enters power down. In this mode, the device will draw less than 25A, the outputs are tri-stated, and the PLL is not running, resulting in a significant reduction of power. The IDT2305 is characterized for both Industrial and Commercial operation.
FUNCTIONAL BLOCK DIAGRAM
8 CLKOU T
PLL REF 1 Control Logic
3
CLK1
2
CLK2
5
CLK3
7 CLK4
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
1
c 2001 Integrated Device Technology, Inc.
APRIL 2001
DSC-5174/2
IDT2305 3.3V ZERO DELAY CLOCK BUFFER
COMMERCIALAND INDUSTRIAL TEMPERATURE RANGES
PIN CONFIGURATION
ABSOLUTE MAXIMUM RATINGS
Symbol VDD VI (2) VI IIK (VI < 0) Rating Supply Voltage Range Input Voltage Range (REF) Input Voltage Range (except REF) Input Clamp Current Continuous Current Maximum Power Dissipation Storage Temperature Range Commercial Temperature Range Industrial Temperature Range
(1)
Unit V V V mA mA mA W C C C
Max. -0.5 to +4.6 -0.5 to +5.5 -0.5 to VDD+0.5 -50 50 100 0.7 -65 to +150 0 to +70 -40 to +85
REF CLK2 CLK1 GND
1 2 3 4 SO8-1
8 7 6 5
CLKOUT CLK4 VDD CLK3
IO (VO = 0 to VDD) Continuous Output Current VDD or GND TA = 55C (in still air) (3) TSTG
SOIC TOP VIEW
Operating Temperature Operating Temperature
NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 3. The maximum package power dissipation is calculated using a junction temperature of 150C and a board trace length of 750 mils.
APPLICATIONS:
* * * * * SDRAM Telecom Datacom PC Motherboards/Workstations Critical Path Delay Designs
PIN DESCRIPTION
Pin Name REF(1) CLK2(2) CLK1(2) GND CLK3(2) VDD CLK4(2) CLKOUT(2)
NOTES: 1. Weak pull down. 2. Weak pull down on all outputs.
Pin Number 1 2 3 4 5 6 7 8 IN Out Out Ground Out PWR Out Out
Type Output clock Output clock Ground Output clock 3.3V Supply Output clock
Functional Description Input reference clock, 5 Volt tolerant input
Output clock, internal feedback on this pin
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IDT2305 3.3V ZERO DELAY CLOCK BUFFER
COMMERCIALAND INDUSTRIAL TEMPERATURE RANGES
OPERATING CONDITIONS - COMMERCIAL
Symbol VDD TA CL CIN Parameter Supply Voltage Operating Temperature (Ambient Temperature) Load Capacitance < 100MHz Load Capacitance 100 - 133MHz Input Capacitance Min. 3 0 -- -- -- Max. 3.6 70 30 10 7 pF Unit V
C
pF
DC ELECTRICAL CHARACTERISTICS - COMMERCIAL
Symbol VIL VIH IIL IIH VOL VOH IDD_PD IDD Parameter Input LOW Voltage Level Input HIGH Voltage Level Input LOW Current Input HIGH Current Output LOW Voltage Output HIGH Voltage Power Down Supply Current Supply Current VIN = 0V VIN = VDD Standard Drive High Drive Standard Drive High Drive REF = 0MHz Unloaded outputs at 66.66 MHz IOL = 8mA IOL = 12mA (- 1H) IOH = -8mA IOH = -12mA (- 1H) -- -- 12 32 A mA 2.4 -- V Conditions Min. -- 2 -- -- -- Max. 0.8 -- 50 100 0.4 Unit V V A A V
SWITCHING CHARACTERISTICS (IDT2305-1) - COMMERCIAL
(1, 2)
Symbol t1
Parameter Output Frequency Duty Cycle = t2 / t1 10pF Load 30pF Load
Conditions
Min. 10 10 40 -- -- -- -- -- -- --
Typ. -- -- 50 -- -- -- 0 0 -- --
Max. 133 100 60 2.5 2.5 250 350 700 200 1
Unit MHz % ns ns ps ps ps ps ms
Measured at 1.4V, FOUT = 66.66MHz Measured between 0.8V and 2V Measured between 0.8V and 2V All outputs equally loaded Measured at VDD/2 Measured at VDD/2 on the CLKOUT pins of devices Measured at 66.66MHz, loaded outputs Stable power supply, valid clock presented on REF pin
t3 t4 t5 t6 t7 tJ tLOCK
Rise Time Fall Time Output to Output Skew Delay, REF Rising Edge to CLKOUT Rising Edge Device-to-Device Skew Cycle-to-Cycle Jitter, pk - pk PLL Lock Time
NOTES: 1. REF Input has a threshold voltage of VDD/2. 2. All parameters specified with loaded outputs.
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IDT2305 3.3V ZERO DELAY CLOCK BUFFER
COMMERCIALAND INDUSTRIAL TEMPERATURE RANGES
SWITCHING CHARACTERISTICS (IDT2305-1H) - COMMERCIAL
(1, 2)
Symbol t1
Parameter Output Frequency Duty Cycle = t2 / t1 Duty Cycle = t2 / t1 10pF Load 30pF Load
Conditions
Min. 10 10 40 45 -- -- -- -- -- 1 -- --
Typ. -- -- 50 50 -- -- -- 0 0 -- -- --
Max. 133 100 60 55 1.5 1.5 250 350 700 -- 200 1
Unit MHz % % ns ns ps ps ps V/ns ps ms
Measured at 1.4V, FOUT = 66.66MHz Measured at 1.4V, FOUT <50MHz Measured between 0.8V and 2V Measured between 0.8V and 2V All outputs equally loaded Measured at VDD/2 Measured at VDD/2 on the CLKOUT pins of devices Measured between 0.8V and 2V using Test Circuit #2 Measured at 66.66MHz, loaded outputs Stable power supply, valid clock presented on REF pin
t3 t4 t5 t6 t7 t8 tJ tLOCK
Rise Time Fall Time Output to Output Skew Delay, REF Rising Edge to CLKOUT Rising Edge Device-to-Device Skew Output Slew Rate Cycle-to-Cycle Jitter, pk - pk PLL Lock Time
NOTES: 1. REF Input has a threshold voltage of VDD/2. 2. All parameters specified with loaded outputs.
OPERATING CONDITIONS - INDUSTRIAL
Symbol VDD TA CL CIN Parameter Supply Voltage Operating Temperature (Ambient Temperature) Load Capacitance < 100MHz Load Capacitance 100 - 133MHz Input Capacitance Min. 3 -40 -- -- -- Max. 3.6 85 30 10 7 pF Unit V
C
pF
DC ELECTRICAL CHARACTERISTICS - INDUSTRIAL
Symbol VIL VIH IIL IIH VOL VOH IDD_PD IDD Parameter Input LOW Voltage Level Input HIGH Voltage Level Input LOW Current Input HIGH Current Output LOW Voltage Output HIGH Voltage Power Down Supply Current Supply Current VIN = 0V VIN = VDD Standard Drive High Drive Standard Drive High Drive REF = 0MHz Unloaded outputs at 66.66 MHz IOL = 8mA IOL = 12mA (- 1H) IOH = -8mA IOH = -12mA (- 1H) -- -- 25 35 A mA 2.4 -- V Conditions Min. -- 2 -- -- -- Max. 0.8 -- 50 100 0.4 Unit V V A A V
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IDT2305 3.3V ZERO DELAY CLOCK BUFFER
COMMERCIALAND INDUSTRIAL TEMPERATURE RANGES
(1,
SWITCHING CHARACTERISTICS (IDT2305-1) - INDUSTRIAL
2)
Symbol t1
Parameter Output Frequency Duty Cycle = t2 / t1 10pF Load 30pF Load
Conditions
Min. 10 10 40 -- -- -- -- -- -- --
Typ. -- -- 50 -- -- -- 0 0 -- --
Max. 133 100 60 2.5 2.5 250 350 700 200 1
Unit MHz % ns ns ps ps ps ps ms
Measured at 1.4V, FOUT = 66.66MHz Measured between 0.8V and 2V Measured between 0.8V and 2V All outputs equally loaded Measured at VDD/2 Measured at VDD/2 on the CLKOUT pins of devices Measured at 66.66MHz, loaded outputs Stable power supply, valid clock presented on REF pin
t3 t4 t5 t6 t7 tJ tLOCK
Rise Time Fall Time Output to Output Skew Delay, REF Rising Edge to CLKOUT Rising Edge Device-to-Device Skew Cycle-to-Cycle Jitter, pk - pk PLL Lock Time
SWITCHING CHARACTERISTICS (IDT2305-1H) - INDUSTRIAL
(1, 2)
Symbol t1
Parameter Output Frequency Duty Cycle = t2 / t1 Duty Cycle = t2 / t1 10pF Load 30pF Load
Conditions
Min. 10 10 40 45 -- -- -- -- -- 1 -- --
Typ. -- -- 50 50 -- -- -- 0 0 -- -- --
Max. 133 100 60 55 1.5 1.5 250 350 700 -- 200 1
Unit MHz % % ns ns ps ps ps V/ns ps ms
Measured at 1.4V, FOUT = 66.66MHz Measured at 1.4V, FOUT <50MHz Measured between 0.8V and 2V Measured between 0.8V and 2V All outputs equally loaded Measured at VDD/2 Measured at VDD/2 on the CLKOUT pins of devices Measured between 0.8V and 2V using Test Circuit #2 Measured at 66.66MHz, loaded outputs Stable power supply, valid clock presented on REF pin
t3 t4 t5 t6 t7 t8 tJ tLOCK
Rise Time Fall Time Output to Output Skew Delay, REF Rising Edge to CLKOUT Rising Edge Device-to-Device Skew Output Slew Rate Cycle-to-Cycle Jitter, pk - pk PLL Lock Time
NOTES: 1. REF Input has a threshold voltage of VDD/2. 2. All parameters specified with loaded outputs.
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IDT2305 3.3V ZERO DELAY CLOCK BUFFER
COMMERCIALAND INDUSTRIAL TEMPERATURE RANGES
ZERO DELAY AND SKEW CONTROL
All outputs should be uniformly loaded in order to achieve Zero I/O Delay. Since the CLKOUT pin is the internal feedback for the PLL, its relative loading can affect and adjust the input/output delay. The Output Load Difference diagram illustrates the PLL's relative loading with respect to the other outputs that can adjust the Input-Output (I/O) Delay. For designs utilizing zero I/O Delay, all outputs including CLKOUT must be equally loaded. Even if the output is not used, it must have a capacitive load equal to that on the other outputs in order to obtain true zero I/O Delay. If I/O Delay adjustments are needed, use the Output Load Difference diagram to calculate loading differences between the CLKOUT pin and other outputs. For zero output-to-output skew, all outputs must be loaded equally.
REF TO CLKA/CLKB RELAY vs. OUTPUT LOAD DIFFERENCE BETWEEN CLKOUT PIN AND CLKA/CLKB PINS
1500
1000
REF to CLKA/CLKB Delay (ps)
500
0 -30 -500 -25 -20 -15 -10 -5 0 5 10 15 20 25 30
-1000
-1500
OUTPUT LOAD DIFFERENCE BETWEEN CLKOUT PIN AND CLKA/CLKB PINS (pF)
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IDT2305 3.3V ZERO DELAY CLOCK BUFFER
COMMERCIALAND INDUSTRIAL TEMPERATURE RANGES
SWITCHING WAVEFORMS
DUTY CYCLE TIMING
t1 t2 1.4V 1.4V 1.4V
OUTPUT TO OUTPUT SKEW
1.4V Output 1.4V t5
Output
ALL OUTPUTS RISE/FALL TIME
Output 0.8V t3 2V 2V 0.8V t4 3.3V 0V
INPUT TO OUTPUT PROPAGATION DELAY
REF VDD/2
Output t6
VDD/2
DEVICE TO DEVICE SKEW
C LK OU T D evice 1 C LK OU T D evice 2 VDD/2
t7
VDD/2
TEST CIRCUITS
TEST CIRCUIT 1
VDD 0.1 F C LO A D VDD 0.1 F GND GND GND GND OUTPUTS 10pF 1K
TEST CIRCUIT 2
VDD 0.1 F OUTPUTS
CLKOUT
1K
CLKOUT
VDD 0.1 F
Test Circuit for all Parameters Except t8 7
Test Circuit for t8, Output Slew Rate On -1H Devices
IDT2305 3.3V ZERO DELAY CLOCK BUFFER
COMMERCIALAND INDUSTRIAL TEMPERATURE RANGES
TYPICAL DUTY CYCLE(1) AND IDD TRENDS(2) FOR IDT2305-1
Duty Cycle vs VDD (for 30pf loads over frequency - 3.3V, 25C) 60 58 56 60 58 56 Du ty C ycle vs VDD (for 10pF load s over frequency - 3.3V, 25C )
Duty Cycle (% )
52 50 48 46 44 42 40 3 3.1 3.2 3.3 3.4 3.5 3.6
33MH z 66MHz 100MHz
Duty Cycle (% )
54
54 52 50 48 46 44 42 40 3 3.1 3.2 3.3 3.4 3.5 3.6
33MHz 66MH z 100M Hz 133M Hz
VDD (V)
Duty Cycle vs Frequency (for 30pf loads over temperature - 3.3V) 60 58 56 60 58 56
VDD (V)
D uty C ycle vs Fre qu ency (for 10pF loads over tem perature - 3.3V)
Duty Cycle (% )
54 52 50 48 46 44 42 40 20 40 60 80 100 120 140
-40C 0C 25C 70C 85C
Duty Cycle (% )
54 52 50 48 46 44 42 40 20 40 60 80 100 120 140
-40C 0C 25C 70C 85C
Frequency (M Hz)
IDD vs Number of Loaded Outputs (for 30pf loads over frequency - 3.3V, 25C) 140 120 100 80 60 140 120 100 80 60
Frequency (M Hz)
IDD vs N um ber of Loade d O utputs (for 10pF loads over frequency - 3.3V, 25C )
IDD (mA)
33MH z 66MHz 100MHz
IDD (mA)
33MH z 66MHz 100MHz
40 20 0 0 2 4 6 8
40 20 0 0 2 4 6 8
Number of Loaded Outputs
Number of Loaded Outputs
NOTES: 1. Duty Cycle is taken from typical chip measured at 1.4V. 2. IDD data is calculated from IDD = ICORE + nCVf, where ICORE is the unloaded current. (n = Number of outputs; C = Capacitance load per output (F); V = Supply Voltage (V); f = Frequency (Hz))
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IDT2305 3.3V ZERO DELAY CLOCK BUFFER
COMMERCIALAND INDUSTRIAL TEMPERATURE RANGES
TYPICAL DUTY CYCLE(1) AND IDD TRENDS(2) FOR IDT2305-1H
Duty C ycle vs VDD (for 30pf loads over frequency - 3.3V, 25C) 60 58 56 60 58 56 D uty C ycle vs VDD (for 10pF load s over frequency - 3.3V, 25C )
Duty C ycle (% )
52 50 48 46 44 42 40 3 3.1 3.2 3.3 3.4 3.5 3.6
33MH z 66MH z 100M Hz
Duty C ycle (% )
54
54 52 50 48 46 44 42 40 3 3.1 3.2 3.3 3.4 3.5 3.6
33MH z 66MH z 100M Hz 133M Hz
VDD (V)
Duty C ycle vs Frequency (for 30pf loads over temperature - 3.3V) 60 58 56 60 58 56
VDD (V)
D u ty C ycle vs Frequ ency (for 10pF loads over tem perature - 3.3V)
Duty C ycle (% )
54 52 50 48 46 44 42 40 20 40 60 80 100 120 140
-40C 0C 25C 70C 85C
Duty C ycle (% )
54 52 50 48 46 44 42 40 20 40 60 80 100 120 140
-40C 0C 25C 70C 85C
Frequency (M H z)
IDD vs N um ber of Loaded O utputs (for 30pf loads over frequency - 3.3V, 25C) 160 140 120 100 160 140 120 100
Frequency (M H z)
IDD vs N um b er of Loa ded O utp uts (for 10pF loads over frequency - 3.3V, 25C )
IDD (m A)
IDD (m A)
80 60
80 60
33MH z 66MH z 100M Hz
33MH z 66MH z 100M Hz
40 20 0 0 2 4 6 8
40 20 0 0 2 4 6 8
N um ber of Loaded O utputs N um ber of Loaded O utputs NOTES: 1. Duty Cycle is taken from typical chip measured at 1.4V. 2. IDD data is calculated from IDD = ICORE + nCVf, where ICORE is the unloaded current. (n = Number of outputs; C = Capacitance load per output (F); V = Supply Voltage (V); f = Frequency (Hz))
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IDT2305 3.3V ZERO DELAY CLOCK BUFFER
COMMERCIALAND INDUSTRIAL TEMPERATURE RANGES
ORDERING INFORMATION
IDT XXXXX Device Type XX Package X Process
Blank I DC
Comm ercial (0 oC to +70 oC) Industrial (-40 o C to +85 o C) Small Outline (SO8-1)
2305-1 2305-1H
Zero Delay Clock Buffer High Drive Output
Ordering Code IDT2305-1DC IDT2305-1DCI IDT2305-1HDC IDT2305-1HDCI 8-Pin SOIC 8-Pin SOIC 8-Pin SOIC 8-Pin SOIC
Package Type Commercial Industrial Commercial Industrial
Operating Range
CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054
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*To search for sales office near you, please click the sales button found on our home page or dial the 800# above and press 2. The IDT logo is a registered trademark of Integrated Device Technology, Inc.
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